Scalable ASIC Design Methodologies for Multi-Chiplet Systems

Abstract

The semiconductor industry is rapidly moving from conventional monolithic System-on-Chip (SoC) designs to chiplet-based architectures as a practical solution driven by mounting design complexity, rising manufacturing costs, and the limits of advanced process scaling. Chiplet-based systems enable heterogeneous integration, i.e., integrating specialised functional blocks manufactured using ent process technologies into a single package, hence  The evolution of multi-chiplet systems increasingly challenges standard ASIC design methodologies by requiring solutions for high-speed interconnects, power delivery, thermal management, verification complexity and advanced packaging integration. This work presents a scalable ASIC design methodology for multi-chiplet systems, focusing on design efficiency, modularity and system-level reliability, while enabling future scalability. The proposed methodology provides a hierarchical and reusable design framework that combines standardised chiplet interfaces, optimal interconnect topologies, power-efficient floorplanning methodologies, and scalable verification tools to improve the development cycle. Co-design methodologies that address the three challenges in the design process at an early stage, i.e. silicon, packaging and thermal challenges, are presented in this study to reduce integration risks along with performance bottlenecks. This study demonstrates the effectiveness of the proposed methodology through a detailed case study of a heterogeneous multi-chiplet computing architecture. The results show significant improvements in design turnaround time, connection efficiency, temperature distribution, and verification coverage over traditional ASIC flows. The results emphasise the benefits of modular reuse and standardised communication protocols, enabling scalable system growth without significantly increasing design complexity. This research opens a path for next-generation semiconductor design by providing a practical and scalable framework for high-performance multi-chiplet ASIC devices. The proposed paradigm offers valuable insights for researchers and industry specialists working on effective heterogeneous integration and innovative semiconductor architectures.